`timescale 1ns / 100ps
`include "value.v"

module value_tb;

//input
reg clkin;
reg aa1;
reg aa2;

//output
wire bb1;
wire bb2;
wire cc1;
wire cc2;
wire dd1;
wire dd2;

value_a a_u(
    .clk(clkin), .a1(aa1), .a2(aa2),
    .b1(bb1), .b2(bb2),
    .c1(cc1), .c2(cc2),
    .d1(dd1), .d2(dd2)
);

integer i;

initial begin
    $display("Testing Value passing start.");
    $dumpfile("value_pass.vcd");
    $dumpvars(0, value_tb);

    // signaling
    clkin = 0;
    
    for ( i = 0; i < 50; i++) begin
        #10
        aa1 = 0;
        aa2 = 0;
        
        #10
        aa1 = 1;
        aa2 = 1;
    end 
    
    $display("Testing done!");
    $finish;
end

always #15 clkin = ~ clkin;

endmodule 

